Risc-V: Security Vulnerabilities
The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.
CVSS Score
9.8
EPSS Score
0.006
Published
2021-08-13